VBUS

GND

ID

12 pF

D+

D-

SEND

/END

MIC

R SPK

L SPK

LP8727

SNVS898A – OCTOBER 2012 – REVISED MAY 2013

www.ti.com

Operation Description

MULTIPLEXING SWITCHES

The LP8727 supports USB High-speed, UART and stereo audio & microphone by providing automatic

multiplexing switches between Micro/Mini USB connector and USB, UART and Audio paths in cellular phone

applications. The LP8727 detects the external devices which can be connected to Micro/Mini USB connector and

informs the processor the detection result by generating an interrupt. But, the LP8727 does not automatically

change the state of switch mux when the external device is detected. The processor is responsible to change the

Figure 2. Stereo Audio & MIC Connection

DEFAULT SWITCH STATUS

The LP8727 can configure default switch connection at startup to either USB or UART by the DSS input. The

DSS input has a 300 k

Ω of internal pulldown resistor. When DSS is logic low (connected to GND or left floating),

the default switch connection is set to USB. For UART startup, the DSS should be pulled high to VBAT through

an external 300 k

Ω pull-up resistor. The status of DSS input is monitored from the startup of device and will be

latched at the first rising edge of SCL input. The status of DSS input is monitored and latched at the 1st rising

edge of sCL input.

HIGH-IMPEDANCE MODE

If the LP8727 is powered from VBAT (VBUS is not present), the default switch connections for D+, D- and ID

should be Hi-Z regardless of DSS status until USB & ID detection is done. The high-impedance mode should

LOW-POWER MODE

The LP8727 is designed to support low-power modes by CP_EN, ADC_EN and SEMREN bits on CONTROL1

register. The ID detection LDO is controlled by either ADC_EN or SEMREN bits.

•

CP_EN: When CP_EN bit is set to ‘1’, the charge pump is enabled and this allows the audio signal inputs

(AUD1 and AUD2) to be driven to negative voltage rail.

•

ADC_EN: When ADC_EN bit is set to ‘1’, ID detection LDO and the internal ADC are enabled. When

ADC_EN is ‘0’, IDNO bits (ADC output) will be 4’h0000 and INT\ will not be asserted. Any pending interrupts

due to a change in the ADC output will not be cleared and must be cleared manually by reading INT_STATx

registers.

•

SEMREN: When SEMREN bit is set to ‘1’, ID detection LDO and the internal comparators for SEND/END and

microphone removal detections are enabled. When SEMREN is ‘0’, the SEND/END and MR_COMP registers

will be set to ‘0’ and INT\ will not be asserted. Any pending interrupts due to a change in the SEND/END or

MR_COMP comparators will not be cleared and must be cleared manually by reading INT_STATx registers.

14

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