UCD3138128APFC datasheet(73/83 Pages) TI1

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UCD3138128A

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SLUSC99 – JULY 2016

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11 Power Supply Recommendations

•

Both 3.3 VD and 3.3 VA should have a local capacitor of at least 4.7-µF in parallel with a 10-nF capacitor

placed as close as possible to the device pins.

•

BP18 should have a 1-µF capacitor in parallel with a 10-nF capacitor to ground.

For detailed practical design guidelines, refer to (SLUA779).

12 Layout

12.1 IC Grounding and Layout Guidelines

•

Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that one

solid SGND is dedicated for return current path, referred to the layout example.

•

Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has

different ESL, Capacitance and ESR, and they have different frequency response.

•

Avoid long traces close to radiation components, and place them into an internal layer, and it is preferred to

have grounding shield.

•

Analog circuits and digital circuits should have separate return to ground; although with a single plane, still try

to avoid mixing analog current and digital current.

•

Do not use a ferrite bead or larger than 3 Ω resistor to connect between V33A and V33D.

•

Both 3.3VD and 3.3VA should have local decoupling capacitors close to the device power pins, add vias to

connect decoupling caps directly to SGND.

•

Avoid negative current/negative voltage on all pins, so Schottky clamping diodes may be needed to limit the

voltage; avoid more than 3.8 V or less than –0.3 V voltage spikes on all pins; add Schottky diodes on the pins

which could have voltage spikes during surge test; be aware that a Schottky has relatively higher leakage

current, which can affect the voltage sensing at high temperature.

•

RESET pin should have one at least 2.2 µF low ESL capacitor locally decoupled with SGND plane. This

capacitor must be located close to the device RESET pin. It is highly recommended to use a small resistance

(such as 220 Ω) to connect the RESET pin with 3.3 VD.

•

If the XTAL_IN (Pin 61) and XTAL_OUT (Pin 62) are not used for external clock, tie them to 1.8V (Pin BP18)

through a 1k

Ω resistor respectively.

For detailed practical design guidelines, refer to (SLUA779).

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