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VSP1221 데이터시트(PDF) 10 Page - Texas Instruments

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부품명 VSP1221
상세설명  12-BIT, 21-MSPS, ULTRALOW-POWER CCD SIGNAL PROCESSOR
PDF  26 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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VSP1221 데이터시트(HTML) 10 Page - Texas Instruments

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SERIAL DATA FORMAT
Standard Functionality
REGISTER DESCRIPTION
(2)
VSP1221
SLES012A – SEPTEMBER 2001 – REVISED JULY 2004
The serial data is always grouped in 16-bit blocks with the following format. Multiple 16-bit blocks can be send
through the SDIN pin (pin 47) keeping SLOAD (pin 46) low.
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
MSB
LSB
RD/WR(1)
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Address
Register Data
(1)
RD/WR = 0, Write into registers, RD/WR = 1, Read from registers
REGISTER ADDRESS
REGISTER NAME
REGISTER FUNCTION
A4
A3
A2
A1
A0
0
0
0
0
0
Control register
Mode control
0
0
0
0
1
PGA register
Gain control
0
0
0
1
0
User DAC1 register
User DAC1 control
0
0
0
1
1
User DAC2 register
User DAC2 control
0
0
1
0
0
Reserved
Reserved
0
0
1
0
1
Reserved
Reserved
0
0
1
1
0
OB register
OB level control
0
0
1
1
1
Blanking register
Blanking output control
0
1
0
0
0
Signal polarity register
Clock signal polarity control
0
1
0
0
1
Timing register 1
ADCCLK
0
1
0
1
0
Timing register 2
SHP
(2)
The register values are updated as soon as the register is written. It may take 0 to 9 ADCCLK cycles for it to have effect on the device.
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