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Timing Register 1

Timing Register 2

(2)

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

SD15

SD0

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

LSB

RD/WR

0

1

0

0

1

Reserved

BYPZ

MSB

ADCDELAY

LSB

Address

Data

BIT

NAME

DEFAULT VALUE

DESCRIPTION

SD0-SD3

ADCDELAY

All 0

Delay ADC clock by programmed value

Delay step = 0.8 ns

Code

Delay

0000

0

0001

0.8 ns

.

.

1110

11.2 ns

1111

12 ns

SD4

BYPZ

1

BYPZ = 1, signal polarity and programmable delay disable

SD5-SD9

Reserved

All 0

Reserved

(1)

When BYPZ = 0, the internal delays of SHP and SHD increases approximately by 3 ns.

SD15

SD0

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

LSB

RD/WR

0

1

0

1

0

Reserved

MSB

SHDDELAY

LSB

MSB

SHPDELAY

LSB

Address

Data

(2)

For this register to take effect, bit SD4 of timing register 1 must be 0 (see the timing register 1 section.

BIT

NAME

DEFAULT

DESCRIPTION

VALUE

SD0-SD3

SHPDELAY

All 0

Delay SHP clock by programmed value

Delay step = 0.8 ns

Code

Delay

0000

0

0001

0.8 ns

.

1110

11.2 ns

1111

12 ns

SD4-SD7

SHDDELAY

All 0

Delay SHD clock by programmed value

Delay step = 0.8 ns

Code

Delay

0000

0

0001

0.8 ns

.

1110

11.2 ns

1111

12 ns

SD8-SD9

Reserved

All 0

Reserved

14