| 전자부품 데이터시트 검색엔진 |
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VSP1221 데이터시트(PDF) 21 Page - Texas Instruments |
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VSP1221 데이터시트(HTML) 21 Page - Texas Instruments |
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21 / 26 page ![]() www.ti.com N N+1 N−9 OB Calibration Cycle DIN (CCD IN) SHP SHD CLPOB BLKG CLPDM ADCCLK D0–D11 N−8 N−7 Optical Black Pixels Dummy Pixels Active Image Pixels 12 Clocks 12 Clocks VSP1221 SLES012A – SEPTEMBER 2001 – REVISED JULY 2004 APPLICATION INFORMATION (continued) A. OB Calibration latency is 12 clocks. So, OB update starts 12 clocks after CLPOB is pulled low and stops 12 clocks after CLPOB is pulled high. B. If active image pixels are located immediately after CLPOB goes high, the OB update will affect the adjacent 12 pixels. C. The device clocks are stopped during BLKG and CLPDM. Therefore, if these signals appear immediately after CLPOB goes high, the OB calibration update for the subsequent 12 clocks will stop. So, its recommended to delay BLKG and CLPDM by at least 12 pixels after CLPOB goes high. Figure 10. System Timing Diagram Example 21 |
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