GD25Q32C datasheet(35/50 Pages) ELM

35 / 50 page

Rev.1.0

50 -

http://www.elm-tech.com

GD25Q32CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash

time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.

The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status

going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the

device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1

immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and

release the suspend state. The command sequence is show below.

Figure 33. Program/Erase Suspend Sequence Diagram

Command

0 1 2 3 4 5 6 7

75H

CS#

SCLK

High-Z

tSUS

Accept read command

7.29. Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program or sector/block erase operation

after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if

the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register

will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or

Block will complete the erase operation or the page will complete the program operation. The Program/Erase

Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in

Figure34.

Figure 34. Program/Erase Resume Sequence Diagram

Command

0 1 2 3 4 5 6 7

7AH

CS#

SCLK

Resume Erase/Program

7.30. Erase Security Registers (44H)

The GD25Q32C provides three 1024-byte Security Registers which can be erased and programmed

individually. These registers may be used by the system manufacturers to store security and other important

information separately from the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)

command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command

GD25Q32C 데이터시트(PDF) 35 Page - ELM Electronics