SI5341_16 datasheet(21/53 Pages) SILABS

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Table 5.3. Input Clock Specifications

(VDD=1.8V ± 5%, VDDA=3.3V ± 5%, TA=-40 to 85°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Standard Input Buffer with Differential or Single-Ended - AC-Coupled (IN0/IN0b, IN1/IN1b, IN2/IN2b, FB_IN/FB_INb)

Input Frequency Range

fIN

Differential

0.008

—

750

MHz

All Single-ended Signals

(including LVCMOS)

0.008

—

250

MHz

Input Voltage Swing1

VIN

Differential AC-coupled

fIN < 250 MHz

100

—

1800

mVpp_se

Differential AC-coupled

250 MHz < fIN < 750 MHz

225

—

1800

mVpp_se

Single-ended AC-coupled

fIN < 250 MHz

100

—

3600

mVpp_se

Slew Rate2, 3

400

—

V/μs

Duty Cycle

—

Input Capacitance

CIN

—

0.3

—

Input Resistance

RIN

—

kΩ

Pulsed CMOS Input Buffer - DC Coupled (IN0, IN1, IN2)4

Input Frequency

fIN

0.008

—

250

MHz

Input Voltage

VIL

–0.2

—

0.4

VIH

0.8

—

Slew Rate2, 3

400

—

V/μs

Duty Cycle

Clock Input

—

Minimum Pulse Width

Pulse Input

1.6

—

Input Resistance

RIN

—

kΩ

REFCLK (Applied to XA/XB)

Input Frequency Range

fIN

Full operating range. Jitter

performance may be re-

duced.

—

200

MHz

Range for best jitter.

—

MHz

Input Single-ended Voltage

Swing

VIN_SE

365

—

2000

mVpp_se

Input Differential Voltage Swing

VIN_DIFF

365

—

2500

mVpp_diff

Slew Rate2, 3

Imposed for best jitter per-

formance

400

—

V/μs

Input Duty Cycle

—

Si5341/40 Rev D Data Sheet

Electrical Specifications

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