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AP0100CS 데이터시트(PDF) 62 Page - ON Semiconductor

부품명 AP0100CS
상세설명  High-Dynamic Range (HDR) Image Signal Processor (ISP)
PDF  73 Pages
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AP0100CS 데이터시트(HTML) 62 Page - ON Semiconductor

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AP0100CS HDR: Image Signal Processor (ISP)
Usage Modes
AP0100CS/D Rev. 6, Pub. 1/16 EN
62
©Semiconductor Components Industries, LLC,2016.
Figure 43:
Frame_Sync (Interlaced Operation) Diagram
Offset Error
OER
±1
% FS
For differental output only
Gain Error
DGER
±2
% FS
Absolute Gain Error
GER
±5
% FS
Table 37:
Frame_Sync (Interlaced Operation) Parameters
Parameter
Name
Conditions
Min
Typ
Max Unit
T_FRAME_SYNC
T_FRAME_SYNC
3
EXTCLK cycles
T_RESYNC
T_RESYNC
NTSC
100
ms
T_RESYNC
T_RESYNC
PAL
120
ms
Table 36:
Video DAC Electrical Characteristics
Default Setup Conditions: fEXTCLK= 27 MHz, VDDIO_H = VDD_OTPM = 2.8V, VDD_REG = VDDIO_S = 1.8V,
VDDA_DAC=3.3V, VDD_DAC=1.2V; TA = 25°C unless otherwise stated
Parameter
Symbol
Min
Typ
Max
Unit
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