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AP0100CS 데이터시트(PDF) 43 Page - ON Semiconductor

부품명 AP0100CS
상세설명  High-Dynamic Range (HDR) Image Signal Processor (ISP)
PDF  73 Pages
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AP0100CS 데이터시트(HTML) 43 Page - ON Semiconductor

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AP0100CS/D Rev. 6, Pub. 1/16 EN
43
©Semiconductor Components Industries, LLC,2016.
AP0100CS HDR: Image Signal Processor (ISP)
Slave Two-Wire Serial Interface (CCIS)
Slave Two-Wire Serial Interface (CCIS)
The two-wire slave serial interface bus enables read/write access to control and status
registers within the AP0100CS.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of
low-level protocol elements, as follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
•data bytes
• a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 16 below. The user can change the slave address by changing a
register value.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes. One
data bit is transferred during each SCLK clock period. SDATA can change when SCLK is low
and must be stable while SCLK is HIGH.
Table 16:
Two-Wire Interface ID Address Switching
SADDR
Two-Wire Interface Address ID
00x90
10xBA



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