ASX340CS datasheet(14/74 Pages) ONSEMI

14 / 74 page

ASX340CS_DS Rev. F Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

SOC Description

Detailed Architecture Overview

Sensor Core

The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable

gain and black offset, and timing and control as illustrated in Figure 4.

Figure 4:

Sensor Core Block Diagram

Pixel Array Structure

The sensor core pixel array is configured as 792 columns by 560 rows, as shown in

Figure 5.

Figure 5:

Pixel Array Description

Black rows used internally for automatic black level adjustment are not addressed by

default, but can be read out in raw output mode through a register setting.

There are 728 columns by 560 rows of optically-active pixels (that is, clear pixels) that

include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects

during color interpolation and correction. Among the 728 columns by 560 rows of clear

Communication

Bus

to IFP

10-Bit Data

to IFP

Sync

Signals

Clock

Control Register

Analog Processing

Active Pixel

Sensor (APS)

Array

Timing and Control

ADC

demosaic rows

Active pixel array

640 x 480

(not to scale)

Pixel logical address = (791, 559)

Pixel logical address = (0, 0)

lens alignment rows

(64, 0)

(104, 36)

(751, 523)

ASX340CS 데이터시트(PDF) 14 Page - ON Semiconductor

ASX340CS 데이터시트(HTML) 14 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

데이터시트 다운로드

링크 URL