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ASX340CS 데이터시트(PDF) 39 Page - ON Semiconductor

부품명 ASX340CS
상세설명  1/4-Inch Color CMOS NTSC/PAL Digital Image SOc
PDF  74 Pages
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ASX340CS 데이터시트(HTML) 39 Page - ON Semiconductor

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ASX340CS_DS Rev. F Pub. 6/15 EN
39
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential READ, Start from Random Location
This sequence (Figure 19) starts in the same way as the single READ from random loca-
tion (Figure 17 on page 32). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 19:
Sequential READ, Start from Random Location
Sequential READ, Start from Current Location
This sequence (Figure 20) starts in the same way as the single READ from current loca-
tion (Figure 18). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 20:
Sequential READ, Start from Current Location
Single Write to Random Location
Figure 21 shows the typical WRITE cycle from the host to the ASX340CS.The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 21:
Single WRITE to Random Location
Read Data
(15:8)
A
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Slave Address
0
S
Sr
A Reg Address[15:8]
A
Reg Address[7:0]
A
Read Data
Slave Address
Previous Reg Address, N
Reg Address, M
M+1
M+2
M+1
M+3
A
1
M+L-2
M+L-1
M+L
A
P
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(7:0)
A
Read Data
Read Data
Previous Reg Address, N
N+1
N+2
N+L-1
N+L
A
Read Data
Slave Address
A
A
1
A
S
P
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
(15:8)
A
Read Data
(7:0)
A
Read Data
Read Data
(15:8)
A
Read Data
(7:0)
Slave Address
0
S
A Reg Address[15:8]
A
Reg Address[7:0]
A
P
Previous Reg Address, N
Reg Address, M
M+1
A
A
Write Data



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