TVP7002IPZP datasheet(2/58 Pages) TI1

2 / 58 page

Output

Formatter

R[9:0]

G[9:0]

Host

Interface

Timing Processor

and

Clock Generation

RIN_1

SCL

SDA

I2CA

GIN_1

BIN_1

Clamp

Gain and

Offset

10-bit

ADC

HSYNC_A

VSYNC_A

COAST

CLAMP

FILT1

SOGIN_1

RESETB

PWDN

B[9:0]

SOGOUT

HSOUT

VSOUT

DATACLK

RIN_2

GIN_2

BIN_2

EXT_CLK

SOGIN_2

HSYNC_B

VSYNC_B

FILT2

RIN_3

GIN_3

GIN_4

SOGIN_3

BIN_3

FIDOUT

Color Space

Conversion

and

4:4:4 to 4:2:2

Conversion

Gain and

Offset

Gain and

Offset

10-bit

ADC

10-bit

ADC

TVP7002

SLES206C – MAY 2007 – REVISED APRIL 2013

www.ti.com

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital

(A/D) converter with clamping functions and variable gain, independently programmable for each channel. The

clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes

analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition,

TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from

the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.

All programming of the device is done via an industry-standard I2C interface, which supports both reading and

writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

Ordering Information(1)

PACKAGED DEVICES

PACKAGE OPTION

100-PIN PLASTIC FLATPACK PowerPAD

TVP7002PZP

Tray

0°C to 70°C

TVP7002PZPR

Reel

(1)

For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

Functional Block Diagram

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