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ST16C552AIJ68 데이터시트(PDF) 12 Page - Exar Corporation |
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ST16C552AIJ68 데이터시트(HTML) 12 Page - Exar Corporation |
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12 / 39 page ![]() 12 ST16C552/552A Rev. 3.40 same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 5 below, shows the selectable baud rate table available when using a 1.8432 MHz external clock input. Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK): Output Output User DLM DLL Baud Rate 16 x Clock 16 x Clock Program Program MCR Divisor Divisor Value Value (Decimal) (HEX) (HEX) (HEX) 50 2304 900 09 00 110 1047 417 04 17 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1200 96 60 00 60 2400 48 30 00 30 4800 24 18 00 18 7200 16 10 00 10 9600 12 0C 00 0C 19.2k 6 06 00 06 38.4k 3 03 00 03 57.6k 2 02 00 02 115.2k 1 01 00 01 |
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