AUIR08152S

9

Rev. A8.0

2015-11-09

Example 2: IGBT gate driving by AUIRS21814S ( or AUIRS2191S) and two AUIR08152S buffer ICs.

AUIRS21814S

(AUIRS2191S)

AUIR08152S

AUIR08152S

Vcc

HIN

LIN

COM

Vb

HO

Vs

LO

Vcch

Veeh

Vcc

IN

LPM

OUTH

OUTL

DC+

Vee

GND

Cb

Zl

Zl

DC-

Rin

Ron

Roff

Roff

Ron

GND

Vee

Vcc

Vcc

LPM

IN

Rin

VccL

VeeL

OUTH

OUTL

15V

15V

7V

7V

Vss

Cb

Figure A-2

The AUIRS21814S (and the AUIRS2191S) have separate Vss and COM pins. They can be simply connected

together or, better, connected to separate logic and power GND.

In any case, the low side AUIR08152S GND pin has to be connected to the low side IGBT emitter, and layouting

care has to be taken that, in case of separate Vss and COM grounding, the imbalance between these two points

doesn’t exceed the data sheet value (usually +/-5V).

Example 3: IGBT gate driving by two AUIRS2117(8)S and two AUIR08152S buffer ICs.

Here, the situation is partially better in term of separation between logic and power GND, in that even the low

side power GND can float -5V to +600V with respect to COM, which is connected to signal GND.

Actually, because the negative Vs transient capability of the AUIRS2117(8) , much more room is allowed for both

positive and negative transients of the IGBT emitters w.r.to COM.