AUIR08152S

10

Rev. A8.0

2015-11-09

AUIR08152S

AUIR08152S

Vcch

Veeh

Vcc

IN

LPM

OUTH

OUTL

DC+

Vee

GND

Cb

Zl

Zl

DC-

Rin

Ron

Roff

Roff

Ron

GND

Vee

Vcc

Vcc

LPM

IN

Rin

VccL

VeeL

OUTH

OUTL

15V

15V

7V

7V

Signal Gnd

Cb

AUIRS2117(8)S

AUIRS2117(8)S

Vb

HO

Vs

Vcc

IN

COM

Vb

HO

Vs

Vcc

IN

COM

Vcc

15V

Figure A-3

Examples of system schematics with Opto

The example in Figure A-4 is, again, a leg gate driver where the AUIR08152 are driven by optocouplers.

The optocoupler only needs to drive a logic signal (the input of the buffer) so there is no need for high current

capability. Its speed mostly depends upon system switching frequency and control aspects. The propagation

delays and rise and fall times of the opto’s stage must preferably be well below the buffer IC ones, to avoid

introducing further delays which affect both the system control loop stability and the modulation depth.

Figure A-4 shows the schematic of one of the leg sections ( high or low ) while Figure A-5 shows the layout.

Figure A-4