ST72734 datasheet(67/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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SYNC PROCESSOR (SYNC) (Cont’d)

4.4.9 Corrector Mode

In this mode, you can perform the following

functions:

– Inhibit pre/post equalization pulses

This removes all pre/post equalization pulses

on the HSYNCO signal.

The inhibition starts on the falling edge of

HSYNCO and lasts for (((HGENR+1)/4)-2)

µs. The decrease of 2µs (one minimum pulse

width) avoids the removal of the next pulse of

HSYNCO.

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

2. Measure the low level of HSYNCO.

3. Set the 2FHINH bit in the CFGR register.

– Extend VSYNCO pulse width by several scan

lines

This function can be also used to extend the

video blanking signal.

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

2. Set the 2FHINH bit in the CFGR register

only if some pre/post equalizations pulses

are detected. (2FHLAT, 2FHDET flags).

3. The extension will be the number of

HSYNCO periods set in the VGENR

4. Reset the VCORDIS bit in the POLR

– Extend VSYNCO width during all post equaliza-

tion pulses.

This function extends the VSYNCO pulse

width when post equalization pulses are

detected (2FHDET bit in the POLR register

and 2FHLAT bit in the LATR register).

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

2. Set the 2FHINH bit in the CFGR register to

remove pre/post equalization pulses.

3. Measure the low level of HSYNCO.

4. Update HGENR =(FFh - (HGENR + 1)) + 4

to add tolerance

5. Write VGENR > 0.

6. Reset the VCORDIS bit in the POLR

7. Set the VEXT bit in the CFGR register.

– Extend VSYNCO pulse width during pre and

post equalization pulses (for test only).

This function allows extending the VSYNCO

pulse width as long as equalization pulses are

detected. (VSYNCO = VSYNCO + 2FHDET).

Procedure:

1. HSYNCO and VSYNCO polarities must be

positive.

2. Set the 2FHINH bit in the CFGR register to

remove pre/post equalization pulses.

3. Measure the low level of HSYNCO.

4. Update HGENR =(FFh - (HGENR + 1)) + 4.

5. Write VGENR > 0.

6. Reset the VCORDIS bit in the POLR register.

7. Set the VEXT bit in the CFGR register.

8. Set the 2FHEN bit in the ENR register.

Notes:

1. When corrector mode is active, the free-running

frequencies generator and analyzer mode must

be disabled.

(HVGEN=0 in ENR register, HACQ=0, VACQ=0

in the CFGR register).

2. If VGENR=0, all VSYNCO correction functions

are disabled except the 2FHEN bit which must

be cleared if VGENR = 0 or VCORDIS = 1.

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