ST72734 datasheet(53/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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16-BIT TIMER (Cont’d)

STATUS REGISTER (SR)

Read Only

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred. To clear this

bit, first read the SR register, then read or

write the low byte of the IC1R (IC1LR) regis-

ter.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then

read or write the low byte of the OC1R

(OC1LR) register.

Bit 5 = TOF

Timer Overflow.

0: No timer overflow (reset value).

1:The free running counter rolled over from

FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low

byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear

TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred.To clear this

bit, first read the SR register, then read or

write the low byte of the IC2R (IC2LR) regis-

ter.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then

read or write the low byte of the OC2R

(OC2LR) register.

Bit 2-0 = Unused.

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the

input capture 1 event).

OUTPUT

COMPARE

HIGH

(OC1HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

OUTPUT

COMPARE

LOW

(OC1LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

ICF1

OCF1

TOF

ICF2

OCF2

MSB

LSB

MSB

LSB

MSB

LSB

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