ST72734 datasheet(26/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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3.5 MISCELLANEOUS REGISTER

MISCELLANEOUS REGISTER (MISCR)

Address: 0009h

—

Read/Write

Reset Value: 0001 0000 (10h)

Bit 7= VSYNCSEL

DDC1 VSYNC Selection.

This bit is set and cleared by software. It is used to

choose the VSYNC signal in DDC1 mode.

0: VSYNCI selected

1: VSYNCI2 selected

Note: VSYNCI 2 is only available for the DDC cell,

not for the SYNC processor cell.

Bit 6= FLY_SYN

Flyback or Synchro Switch.

This bit is set and cleared by software. It is used to

choose the signals the Timing Measurement Unit

(TMU) will analyse.

0: horizontal and vertical synchro outputs analysis

1: horizontal and vertical Flyback inputs analysis

Bit 5= HSYNCDIVEN

HSYNCDIV Enable.

This bit is set and cleared by software. It is used to

enable the output of the HSYNCO output on PC0.

0: HSYNCDIV disabled

1:HSYNCDIV enabled

Bit 4= FAST

Fast Mode.

This bit is set and cleared by software. It is used to

select the external clock frequency. If the external

clock frequency is 12 MHz, this bit must be at 0,

else if the external frequency is 24 MHz, this bit

must be at 1.

Bit 3= ITBLAT

Falling Edge Detector Latch.

This bit is set by hardware when a falling edge

occurs on pin ITB/PD4 in Port D. An interrupt is

generated if ITBITE=1and the I bit in the CC

0: No falling edge detected on ITB

1: Falling edge detected on ITB

Bit 2= ITALAT

Falling Edge Detector Latch.

This bit is set by hardware when a falling edge

occurs on pin ITA/PD3 in Port D. An interrupt is

generated if ITAITE=1and the I bit in the CC

0: No falling edge detected on ITA

1: Falling edge detected on ITA

Bit 1= ITBITE

ITB Interrupt Enable.

This bit is set and cleared by software.

0: ITB interrupt disabled

1: ITB interrupt enabled

Bit 0= ITAITE

ITA Interrupt Enable.

This bit is set and cleared by software.

0: ITA interrupt disabled

1: ITA interrupt enabled

VSYNC

SEL

FLY_S

HSYNC

DIVEN

FAST ITBLAT ITALAT ITBITE ITAITE

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