MYX29GL01GS11DPIV2 datasheet(43/68 Pages) MICROSS

43 / 68 page

MYX29GL01GS11DPIV2

Revision 1.0 - 01/26/2015

*Advanced information. Subject to change without notice.

1Gb GL-S MirrorBit® Eclipse™

Flash Memory

MYX29GL01GS11DPIV2*

Form #: CSI-D-685 Document 001

8 .4

Read

8.4.1

Read With Output Disable

WhentheCE#signalisassertedLow,thehostsystemmemorycontrollerbeginsareadorwritedatatransfer.

OftenthereisaperiodatthebeginningofadatatransferwhenCE#isLow,Addressisvalid,OE#isHigh,and

WE#isHigh.DuringthisstateareadaccessisassumedandtheRandomReadprocessisstartedwhilethe

dataoutputsremainathighimpedance.IftheOE#signalgoesLow,theinterfacetransitionstotheRandom

Readstate,withdataoutputsactivelydriven.IftheWE#signalisassertedLow,theinterfacetransitionsto

theWritestate.Note,OE#andWE#shouldneverbeLowatthesametimetoensurenodatabuscontention

betweenthehostsystemandmemory.

8.4.2

Random (Asynchronous) Read

WhenthehostsysteminterfaceselectsthememorydevicebydrivingCE#Low,thedeviceinterfaceleavesthe

Standbystate.IfWE#isHighwhenCE#goesLow,arandomreadaccessisstarted.Thedataoutputdepends

ontheaddressmapmodeandtheaddressprovidedatthetimethereadaccessisstarted.

ThedataappearsonDQ15-DQ0whenCE#isLow,OE#isLow,WE#remainsHigh,addressremainsstable,

andtheasynchronousaccesstimesaresatisfied.Addressaccesstime(tACC)isequaltothedelayfromstable

addressestovalidoutputdata.Thechipenableaccesstime(tCE)isthedelayfromstableCE#tovaliddataat

theoutputs.InorderforthereaddatatobedrivenontothedataoutputstheOE#signalmustbeLowatleast

theoutputenabletime(tOE)beforevaliddataisavailable.

AtthecompletionoftherandomaccesstimefromCE#active(tCE),addressstable(tACC),orOE#active(tOE),

whicheveroccurslatest,thedataoutputswillprovidevalidreaddatafromthecurrentlyactiveaddressmap

mode.IfCE#remainsLowandanyoftheAMAXtoA4addresssignalschangetoanewvalue,anewrandom

readaccessbegins.IfCE#remainsLowandOE#goesHightheinterfacetransitionstotheReadwithOutput

Disablestate.IfCE#remainsLow,OE#goesHigh,andWE#goesLow,theinterfacetransitionstotheWrite

state.IfCE#returnsHigh,theinterfacegoestotheStandbystate.BacktoBackaccesses,inwhichCE#

remainsLowbetweenaccesses,requiresanaddresschangetoinitiatethesecondaccess.

SeeSection10.3.1:AsynchronousReadOperations(page54).

8.4.3

Page Read

AfteraRandomReadaccessiscompleted,ifCE#remainsLow,OE#remainsLow,theAMAXtoA4address

signalsremainstable,andanyoftheA3toA0addresssignalschange,anewaccesswithinthesamePage

begins.ThePageReadcompletesmuchfaster(tPACC)thanaRandomReadaccess.

MYX29GL01GS11DPIV2 데이터시트(PDF) 43 Page - Micross Components