UCS1002-2 datasheet(28/114 Pages) MICROCHIP

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Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13)

SMSC UCS1002

DATASHEET

4.2

SMBus Operating Mode

When the COMM_SEL / ILIM pin is connected to directly to ground or though a pull-down resistor with

a value of 33k

Ω or below as listed in Table 4.1, "UCS1002 Communication Mode and ILIM Selection",

the UCS1002 communicates via the SMBus or I2C communications protocols.

APPLICATION NOTE: Upon power-up, the UCS1002 will not respond to any SMBus communications for 5.5 ms.

After this time, full functionality is available.

APPLICATION NOTE: When in the Sleep state, the first SMBus read command sent to the UCS1002 device

address will wake it. Any data sent to the UCS1002 will be ignored and any data read from

the UCS1002 should be considered invalid. The UCS1002 will be fully functional 3 ms after

this first read command is sent. See Section 5.1.2.

4.2.1

System Management Bus

In SMBus mode, the UCS1002 communicates with a host controller, such as an SMSC SIO. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported;

however, the UCS1002 will not stretch the clock signal.

4.2.1.1

SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus clock line is in a logic ‘1’ state.

4.2.1.2

SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus host is reading data from the client device.

The SMBus address is determined based on the resistor connected on the SEL pin as shown in

Table 4.2.

APPLICATION NOTE: If it is necessary to connect the SEL pin to VDD via a resistor, the pull-up resistor may be

any value up to 100 k

Ω.

Figure 4.1 SMBus Timing Diagram

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

T HD:STA

T SU:STO

T HD:STA

T HD:DAT

T SU:DAT

T SU:STA

T FALL

T RISE

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