LAN8740 datasheet(33/136 Pages) MICROCHIP

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DS00001987A-page 33

LAN8740A/LAN8740Ai

3.7

Configuration Straps

Configuration straps allow various features of the device to be automatically configured to user defined values. Config-

uration straps are latched upon Power-On Reset (POR) and pin reset (nRST). Configuration straps include internal

resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected

to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it

reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an

external resistor.

3.7.1

PHYAD[2:0]: PHY ADDRESS CONFIGURATION

The PHYAD[2:0] configuration straps are driven high or low to give each PHY a unique address. This address is latched

into an internal register at the end of a hardware reset (default = 000b). In a multi-transceiver application (such as a

repeater), the controller is able to manage each transceiver via the unique address. Each transceiver checks each man-

agement data frame for a matching address in the relevant bits. When a match is recognized, the transceiver responds

to that particular frame. The PHY address is also used to seed the scrambler. In a multi-transceiver application, this

ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the fre-

quency spectrum.

The device’s SMI address may be configured using hardware configuration to any value between 0 and 7. The user can

configure the PHY address using Software Configuration if an address greater than 7 is required. The PHY address can

be written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Reg-

ister. The PHYAD[2:0] configuration straps are multiplexed with other signals as shown in Table 3-5.

Note:

The system designer must guarantee that configuration strap pins meet the timing requirements specified

in Section 5.6.2, "Power-On nRST & Configuration Strap Timing". If configuration strap pins are not at the

correct voltage level prior to being latched, the device may capture incorrect strap values.

Note:

When externally pulling configuration straps high, the strap should be tied to VDDIO, except for REGOFF

and nINTSEL which should be tied to VDD2A.

TABLE 3-5:

PIN NAMES FOR ADDRESS BITS

Address Bit

Pin Name

PHYAD[0]

RXER/RXD4/PHYAD0

PHYAD[1]

RXCLK/PHYAD1

PHYAD[2]

RXD3/PHYAD2

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