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LAN8740 데이터시트(PDF) 90 Page - Microchip Technology

부품명 LAN8740
상세설명  Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR짰 Technology
PDF  136 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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LAN8740 데이터시트(HTML) 90 Page - Microchip Technology

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LAN8740A/LAN8740Ai
DS00001987A-page 90
2013-2015 Microchip Technology Inc.
4.3.7
WAKEUP CONTROL AND STATUS REGISTER (WUCSR)
Index (In Decimal):
3.32784
Size:
16 bits
Bits
Description
Type
Default
15
Interface Disable
0 = MII/RMII interface enabled
1 = MII/RMII interface disabled. Outputs driven to a low level and inputs
ignored.
R/W
NASR
0b
14:13
LED1 Function Select
00 = LED1 functions as Link/Activity.
01 = LED1 functions as nINT.
10 = LED1 functions as nPME.
11 = LED1 functions as Link Speed.
Note:
Refer to Section 3.8.1, "LEDs" for additional information.
R/W
NASR
0b
12:11
LED2 Function Select
00 = LED2 functions as Link Speed.
01 = LED2 functions as nINT.
10 = LED2 functions as nPME.
11 = LED2 functions as Link/Activity.
Note:
Refer to Section 3.8.1, "LEDs" for additional information.
R/W
NASR
0b
10
RXD2/RMIISEL Function Select
0 = RXD2/RMIISEL pin functions normally as RXD2/RMIISEL.
1 = RXD2/RMIISEL pin functions as nPME.
Note:
Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional infor-
mation.
R/W
NASR
0b
9
nPME Self Clear
0 = nPME pin is not self clearing.
1 = nPME pin is self clearing.
Note:
When set, the de-assertion delay of the nPME signal is controlled
by the nPME Assert Delay bit of the Miscellaneous Configuration
Register (MCFGR). Refer to Section 3.8.4, "Wake on LAN (WoL)"
for additional information.
R/W
NASR
0b
8
WoL Configured
This bit may be set by software after the WoL registers are configured. This
sticky bit (and all other WoL related register bits) is reset only via a power
cycle or a pin reset, allowing software to skip programming of the WoL regis-
ters in response to a WoL event.
Note:
Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional infor-
mation.
R/W/
NASR
0b
7
Perfect DA Frame Received (PFDA_FR)
The MAC sets this bit upon receiving a valid frame with a destination address
that matches the physical address.
R/WC/
NASR
0b
6
Remote Wakeup Frame Received (WUFR)
The MAC sets this bit upon receiving a valid remote Wakeup Frame.
R/WC/
NASR
0b
5
Magic Packet Received (MPR)
The MAC sets this bit upon receiving a valid Magic Packet.
R/WC/
NASR
0b
4
Broadcast Frame Received (BCAST_FR)
The MAC Sets this bit upon receiving a valid broadcast frame.
R/WC/
NASR
0b



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