STM32F413RHT6 datasheet(19/207 Pages) STMICROELECTRONICS

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STM32F413xG/H

Functional overview

3.1

ARM® Cortex®-M4 with FPU core with embedded Flash and

SRAM

The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The ARM® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an ARM core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

The STM32F413xG/H devices are compatible with all ARM tools and software.

Figure 4 shows the general block diagram of the STM32F413xG/H.

Note:

Cortex®-M4 with FPU is binary compatible with Cortex®-M3.

3.2

Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance

advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which

normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 125 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 100 MHz.

3.3

Enhanced Batch Acquisition mode (eBAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It

enables data acquisition through any communication peripherals directly to memory using

the DMA in reduced power consumption as well as data processing while the rest of the

system is in low-power mode (including the Flash and ART). For example in an audio

system, a smart combination of PDM audio sample acquisition and processing from the

DFSDM directly to RAM (Flash and ART

™ stopped) with the DMA using BAM followed by

some very short processing from Flash allows to drastically reduce the power consumption

of the application.

The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed

through the Ibus and Dbus, thus improving code execution performance.

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