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LAN89730 데이터시트(PDF) 201 Page - Microchip Technology

부품명 LAN89730
상세설명  Implements Reduced Power Operating Modes
PDF  218 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN89730 데이터시트(HTML) 201 Page - Microchip Technology

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 2013-2015 Microchip Technology Inc.
DS60001348A-page 201
LAN89730
7.6.3
POWER-ON CONFIGURATION STRAP VALID TIMING
Figure 7-3 illustrates the configuration strap valid timing requirement in relation to power-on. In order for valid configu-
ration strap values to be read at power-on, the following timing requirements must be met.
7.6.4
RESET AND CONFIGURATION STRAP TIMING
Figure 7-4 illustrates the nRESET pin timing requirements and its relation to the configuration strap pins and output
drive. Assertion of nRESET is not a requirement. However, if used, it must be asserted for the minimum period specified.
FIGURE 7-3:
POWER-ON CONFIGURATION STRAP VALID TIMING
TABLE 7-16:
POWER-ON CONFIGURATION STRAP VALID TIMING
Symbol
Description
Min.
Typ.
Max.
Unit
tcfg
Configuration strap valid time
15
ms
Note:
For proper operation in applications where brown-outs may occur, use of an external reset circuit is recom-
mended.
FIGURE 7-4:
nRESET RESET PIN TIMING
TABLE 7-17:
nRESET RESET PIN TIMING VALUES
Symbol
Description
Min.
Typ.
Max.
Unit
trstia
nRESET input assertion time
1
µs
tcss
Configuration strap pins setup to nRESET deassertion
400
ns
tcsh
Configuration strap pins hold after nRESET deassertion
10
ns
VDD33IO
Configuration Straps
tcfg
2.0 V
tcss
nRESET
Configuration
Strap Pins
trstia
tcsh



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