CS86 Series

14

s INPUT/OUTPUT PIN CAPACITANCE

Note : Capacitance varies according to the package and the location of the pin.

s DESIGN METHOD

The integrated standard-cell design environment, SCCAD2, provided for conventional models now supports the

CS86 series. This allows you to design ASICs that operate at up to 500 MHz with up to 40 million gates and to

halve the layout design period. The Fujitsu’s tool GLOSCAD also supports the satandard cell design for CS86

series.

• Physical Synthesis

Physical Synthesis tool support is provided on a consulting business basis. A conventional style of ASIC devel-

opment has a problem that iterations between logic synthesis and layout processing are caused by wiring

congestion and the difference between actual and estimated wiring capacities. Supporting logic synthesis based

on physical information reduces such iterations and contributes to convergence of ASIC design within the

scheduled development period.

• Low Power Synthesis

The Low Power Synthesis tool is supported, which enables the use of gated clock buffers of hard macro type

incorporating sequential cells, such as latches. The use of gated clock buffers of hard macro type provides low

power consumption by the clock line. It also provides reliable operation, reduction in script complexity, and shorter

turnaround time (TAT) for processing.

• Timing Driven Layout

Performing automatic placement and wiring based on chip-level timing constraints. This prevents post-layout

timing problems from developing, which are prominent in particular in the field of deep submicron designs. In

addition, all of remaining timing errors are automatically corrected by the Fujitsu’s automatic timing correction

system. This shortens the development time from the end of creating a net list to the beginning of the prototyping

stage.

• Hierarchical Design

A top-down hierarchical design approach is taken consistently from logic design to physical design to support

larger-scale circuit integration based on deep submicron designing. This enables multiple blocks to be designed

logically and physically at the same time and timing convergence to be attained in a short period, providing a

design environment capable of easily supporting ultra-large-scale integration of circuits.

• Support for Signal Integrity

Automated power wiring enables layout satisfying the design specifications within a short period.

The power width automatic adjustment function designed taking account of internal power consumption and

clock frequencies can produce chips satisfying the current density and voltage drop restrictions without human

intervention. Also, a verification system is prepared to check the signal noise or delay penalty owing to capacitive

coupling between signal conductors and the voltage drop caused by simultaneous local switching.

Parameter

Symbol

Requirements

Unit

Input pin



CIN

Max 16

pF

Output pin

L, M, H, V type

COUT

Max 16

pF

I/O pin

L, M, H, V type

CI/O

Max 16

pF