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LP3928 데이터시트(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 LP3928
상세설명  High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator
PDF  11 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP3928 데이터시트(HTML) 6 Page - National Semiconductor (TI)

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Electrical Characteristics Unless otherwise specified: H = V
IH min, L = VIL max, CVBAT = 1 µF, IOUT = 1 mA,
CVCCB = 1 µF, CVCCA = 1 µF. Typical values and limits appearing in standard typeface apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Note 9) (Continued)
Level Shifter DC Current Levels (Continued)
Unless otherwise specified: EN1 = H, EN2 = X; V
BAT = 6VorVCCA = 1.95V as applicable to B or A respectively.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
BCOM
Common Static Level-Shifter
I
CCB Current (Notes 15, 17)
400
750
µA
I
A
Static Level-Shifter I
CCA
Current (Notes 16, 17)
90
165
µA
I
CCBEXT
Off State I
CCB Current with
External V
CCB (Note 7)
V
BAT=3.6V, EN1=L, EN2=L
15
µA
I
OFFA
Off State V
CCA Current
V
CCA=1.9V, EN1,2=0, Ai=0V, Bi=0V,
DIRi=0V, LatchClk=0V
1.5
5
µA
I
OFFBAT
Off State V
BAT Current
EN1,2=L
0.005
3
µA
I
OZA
Output Leakage Current Ai
V
CCA=1.9V, ViA=0/1.9V, EN1=L
0.001
±2
µA
I
OZB
Output Leakage Current Bi
Vi
B=0V, VBAT=3.35V, VCCB=0, EN1=L
0.001
±2
µA
Vi
B=2.95V, VBAT=3.35V, VCCB=2.95V,
EN1=L
0.001
±2
µA
I
SCA
Short Circuit Current/ Channel
Ai Output, V
CCA=1.9V,
DIRi=L, EN2=L
Ai=0V, Bi=H
−27
−17
mA
Ai=V
CCA, Bi=L
36
56
mA
I
SCB
Short Circuit Current/ Channel
Bi Output, V
BAT=2.95V,
DIRi=H
Bi=0V, Ai=H
−90
−58
mA
Bi=2.95V, Ai=L
60
90
mA
Level Shifter AC Electrical Characteristics
Unless otherwise specified: EN1 = H, 3.05V
≤ V
BAT
≤ 6V, 1.65V ≤ V
CCA = 1.95V. ((Note 28), (Note 29))
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
Propagation Delay A
n to Bn or Bn to An
C
LB = 35 pF, CLA =15 pF
4
7
ns
t
PLH
C
LB = 35 pF, CLA =15 pF
4
7
ns
t
R
Rise Time
C
LB = 35 pF, CLA =15 pF
2
4
ns
t
F
Fall Time
C
LB = 35 pF, CLA =15 pF
2
4
ns
t
MATCH
Delay Differences between Channel Outputs at
Identical Input Signals
1.5
ns
t
SL
Latch Set Up Time
1
2
ns
t
HL
Latch Hold Time
1
2
ns
t
LS
Level-Shifter Mode Switch Response Time
(Note 18)
100
ns
t
DIR
Level-Shifter Direction Switch Response Time
(Note 19)
20
ns
LDO Electrical Characteristics
Unless otherwise specified: EN1 = L, EN2 = H; V
OUTnom = 2.85V, VBAT =VOUT(nom) + 0.5V.
Symbol
Parameter
Conditions
Typical
Limit
Units
Min
Max
∆V
OUT
Output Voltage Tolerance
I
OUT = 1 mA
−2
−3
2
3
%of
V
OUT(nom)
Line Regulation Error (Note 20)
V
BAT =(VOUT(nom) + 0.5V) to 6.0V,
I
OUT =1 mA
−0.10
0.10
%/V
Load Regulation Error (Note 21)
I
OUT = 1 mA to 150 mA
0.005
%/mA
Output AC Line Regulation
V
BAT =VOUT(nom) + 1V,
I
OUT = 100 mA,
C
OUT = 4.7 µF (Figure 1)
1.5
mV
PP
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