I

Note 18: This is the time it takes either to switch the level shifter on or off, or the time it takes to turn the latch by-pass on/off.

Note 19: This is the time it takes to switch the direction of the level shifter. After this time a signal can be applied on the new input. For the B

→A direction, if EN2=1,

the latch set-up time has to be considered separately.

Note 20: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa.

Note 21: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa.

Note 22: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its normal value. This specification does not apply

for input voltages below 2.7V.

Note 24: Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design.

Note 25: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design.

Note 26: The built-in thermal shut-down of the LDO is also used to put all Ai and Bi outputs in tristate mode.

Note 27: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).

Note 28: Unused inputs must be terminated.

Note 29: This electrical specification is guaranteed by design.

C

Level Shifter Propagation Delay A

→B

Level Shifter Propagation Delay B

→A

20039109

20039110

20039106

FIGURE 1. Output AC Line Regulation

20039107

FIGURE 2. PSRR Input Perturbation

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