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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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T89C5115-RATIM 데이터시트(PDF) 80 Page - ATMEL Corporation |
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T89C5115-RATIM 데이터시트(HTML) 80 Page - ATMEL Corporation |
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80 / 105 page  80 T89C5115 4128A–8051–04/02 Table 54. Selected Analog Input Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range! (see section “AC-DC”) Clock Selection The ADC clock is the same as CPU. The maximum clock frequency for ADC is 700 KHz. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. Figure 38. A/D Converter Clock ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 uW. SCH2 SCH1 SCH0 Selected Analog input 000 AN0 001 AN1 010 AN2 011 AN3 100 AN4 101 AN5 110 AN6 111 AN7 Prescaler ADCLK A/D Converter ADC Clock CPU CLOCK CPU Core Clock Symbol ÷ 2 |
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