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T89C5115-RATIM 데이터시트(PDF) 85 Page - ATMEL Corporation |
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T89C5115-RATIM 데이터시트(HTML) 85 Page - ATMEL Corporation |
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85 / 105 page ![]() 85 T89C5115 4128A–8051–04/02 Table 60. Priority Level Bit Values A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see Table 61. Table 61. Interrupt Priority Within Level IPH.x IPL.x Interrupt Level Priority 0 0 0 (Lowest) 01 1 10 2 1 1 3 (Highest) Interrupt Name Interrupt Address Vector Priority Number external interrupt (INT0) 0003h 1 Timer0 (TF0) 000Bh 2 external interrupt (INT1) 0013h 3 Timer1 (TF1) 001Bh 4 PCA (CF or CCFn) 0033h 5 UART (RI or TI) 0023h 6 Timer2 (TF2) 002Bh 7 ADC (ADCI) 0043h 8 |
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