WM8756

Advance Information

AI Rev 1.3 October 2001

19

The REV[2:0] bits are used to invert the phase of the DAC outputs. REV0 controls phase of DAC0, REV1

controls phase of DAC1 and REV2 controls phase of DAC2.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000011

Interface Control

8:6

REV[2:0]

000

Output phase direction

1 in bit 6 reverses OUT0L/R.

1 in bit 7 reverses OUT1L/R.

1 in bit 8 reverses OUT2L/R.

MUTE MODES

Setting the MUTE register bit will apply a 'soft' mute to the input of the digital filters:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

0

MUTE

0

Soft Mute select

0 : Normal Operation

1: Soft mute all channels

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

0

0.001

0.002

0.003

0.004

0.005

0.006

Time(s)

Figure 12 Application and Release of Soft Mute

Figure 12 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at

48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay

constant of approximately 64 input samples. If MUTE is applied for 1024 or more input samples, the

bit. When MUTE is de-asserted, the output will restart almost immediately from the current input sample.

Note that all other means of muting the DAC channels (setting the PL[3:0] bits to 0, setting the PDWN bit

or setting attenuation to 0) will cause much more abrupt muting of the output.

Setting the IZD register bit will enable the internal analogue mute feature:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

4

IZD

0

Internal Analogue Mute Disable

0 : Disable Analogue Mute

1: Enable Analogue Mute