WM8756

Advance Information

AI Rev 1.3 October 2001

26

DSDB MODE SELECT

This pin puts the device into DSD mode when taken low. Due to the nature of DSD operation only a single

software controlled function is available in this mode. This is the PDWN bit.

DSDB

DSD MODE

0

Device in DSD mode

1

Device in normal PCM operation

Table 18 DSD mode Control

DSD DIGITAL AUDIO INTERFACE

DSD mode is selected by taking the DSDB pin low. In this mode the internal digital filters are by-passed,

and the already modulated bitstream data is applied directly to the Switched Capacitor DAC filter where it

is converted and low-pass filtered.

Two formats are supported for data transfer, NORMAL or PHASE MODULATED.

In Normal mode, DSD data is simply clocked into the device using the rising edge of the 64fs DSDCLK64

signal (see Figure 3).

In Phase Modulation mode, the data is supplied in Manchester encoded form (a bit transition occurs

during every data bit, which shapes the spectral energy minimising corruption of the analogue outputs). A

secondary clock DSDCLK128, at 128fs is used to simplify data recovery, the data simply being clocked

with the falling edge of DSDCLK128 when DSDCLK64 is low (see Figure 4).

Operation of PHASE

MODULATED mode is auto-detected by the presence of a clock signal on the DSDCLK128 pin.

DSD clocks are either inputs (when DMSLV = ‘0’) or outputs (when DMSLV = ‘1’). When DMSLV is ‘1’ the

clocks are derived by using the SCKI as detailed below:

DMCKSEL

DSDCLK64

DSDCLK128

0

SCKI/4

SCKI/2

1

SCKI/6

SCKI/3

Table 19 Master/Slave clock selection

DMSLV

CLOCKS

0

inputs

1

outputs

Table 20 Master/Slave function

See Figure 3 and Figure 4 for details of DSD interface timing