| 전자부품 데이터시트 검색엔진 |
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LMX2364SLEX 데이터시트(PDF) 20 Page - National Semiconductor (TI) |
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LMX2364SLEX 데이터시트(HTML) 20 Page - National Semiconductor (TI) |
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20 / 39 page ![]() Test Setup Procedures Sensitivity 20050674 Frequency Input Pin DC Blocking Capacitor Corresponding Counter Default Counter Value MUX Value OSCinIF 1 nF IF_R/RF_R 5000 9 (IF R/2) FinIF 100 pF IF_N 5000 10 (IF N/2) OSCinRF 1 nF RF_R 50 11 (RF R/2) FinRF 100 pF RF_N 50 12 (RF N/2) Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz or more of its expected value. It is typically measured over frequency, voltage, and temperature. In order to test sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value isthen programmed to a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the Ftest/LD pin should be the signal generator frequency divided by twice the correspond- ing counter value. The factor of two comes in because the LMX2364 has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance. In order to perform the measurement, the temperature, fre- quency, and voltage is set to a fixed value and the power level of the signal is varied. Note that the power level at the part is assumed to be 4 dB less than the signal generator power level. This accounts for 1 dB for cable losses and 3 dB for the pad. The power level range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is re- corded for the sensitivity limits. The temperature, frequency, and voltage can be varied in order to produce a family of sensitivity curves. Since this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of the PLL (RF or IF) is powered down when not being tested. For this part, there are actually four frequency input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are show above. www.national.com 20 |
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