35

Table 12. Serial Port Timing

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNIT

2

Serial port clock period (BRR > 8002H)

typical

ns

t

XLXH

1

Serial port clock falling edge to rising edge

(BRR > 8002H)

ns

t

XLXL

2

Serial port clock period (BRR = 8001H)

4 T

OSC

typical

ns

1

Serial port clock falling edge to rising edge

(BRR = 8001H)

ns

1

Output data valid to clock rising edge

ns

1

Output data hold after clock rising edge

2 T

ns

t

XHQV

1

Next output data valid after clock rising edge

ns

1

Input data setup to clock rising edge

ns

1

Input data hold after clock rising edge

0

ns

t

XHQZ

1

Last clock rising to output float

ns

TXD

RXD (OUT)

RXD (IN)

0

1

2

3

4

5

6

7

Figure 12. Serial Port Waveform - Shift Register Mode

0

1

2

3

5

4

6

7

6

Note :

1. Tested only at initial qualification, and after my design or process changes which may affect this characteristic.

2. These specs are verified functional vectors (strobed) only.