UT80C196 datasheet(18/42 Pages) AEROFLEX

18 / 42 page

TUQ

P1.5

---

Port 1 Pin 5. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.5 function of pin 30.

TUO

BREQ

Low

Bus Request. The BREQ output signal asserts during a HOLD

cycle when the internal bus controller has a pending external

memory cycle.

During a HOLD cycle, BREQ will not be asserted until the

HLDA signal is asserted. Once asserted, BREQ does not deas-

sert until the HOLD signal is released.

Setting WSR.7 = 1 enables the BREQ function of pin 30.

TUQ

P1.6

---

Port 1 Pin 6. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.6 function of pin 31.

TUO

HLDA

Low

Bus Hold Acknowledge. The UT80C196KD asserts the HLDA

signal as a result of another device activating the HOLD signal.

By asserting this signal, the UT80C196KD is indicating that it

has released the bus.

Setting WSR.7 = 1 enables the HLDA function of pin 31.

TUQ

P1.7

---

Port 1 Pin 7. A quasi-bidirectional port pin that is read and writ-

ten at location 0Fh of HWindow 0.

Setting WSR.7 = 0 enables the P1.7 function of pin 32.

TUI

HOLD

Low

Bus Hold. The HOLD signal is used to request control of the

bus by another DMA device.

Setting WSR.7 = 1 enables the HOLD function of pin 32.

TUQ

P2.6

---

Port 2 Pin 6. A quasi-bidirectional port pin that is read and writ-

ten at location 10h of HWindow 0.

Setting IOC2.1 = 0 enables the P2.6 function of pin 33.

TUI

T2UP-DN

---

Timer 2 Up or Down. The T2UP-DN pin will dynamically

change the direction that Timer 2 counts.

T2UP-DN = 1 then Timer 2 counts down.

T2UP-DN = 0 then Timer 2 counts up.

Setting IOC2.1 = 1 enables the T2UP-DN function of pin 33.

When IOC2.1 = 0, Timer 2 will only count up.

Table 10: 68-lead Flat Pack Pin Descriptions

QFP Pin#

I/O

Name

Active

Description

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