전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

WTS701EM/T 데이터시트(PDF) 9 Page - Winbond

부품명 WTS701EM/T
상세설명  WINBOND SINGLE-CHIP TEXT-TO-SPEECH PROCESSOR
PDF  77 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WINBOND [Winbond]
홈페이지  http://www.winbond.com
Logo WINBOND - Winbond

WTS701EM/T 데이터시트(HTML) 9 Page - Winbond

Back Button WTS701EM/T Datasheet HTML 5Page - Winbond WTS701EM/T Datasheet HTML 6Page - Winbond WTS701EM/T Datasheet HTML 7Page - Winbond WTS701EM/T Datasheet HTML 8Page - Winbond WTS701EM/T Datasheet HTML 9Page - Winbond WTS701EM/T Datasheet HTML 10Page - Winbond WTS701EM/T Datasheet HTML 11Page - Winbond WTS701EM/T Datasheet HTML 12Page - Winbond WTS701EM/T Datasheet HTML 13Page - Winbond Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 77 page
background image
WTS701
Publication Release Date: May 2003
- 9 -
Revision 3.09
6. PIN DESCRIPTION
Table 1. WTS701 Pin Signal Assignment.
PIN NO.
SYMBOL
I/O
FUNCTION
2,36,44
VSSA
G
Analog Ground pins.
3
VCLK
I
CODEC master clock
4
VFS
I
CODEC frame synchronization signal
5
VDX
O
CODEC data output. This pin puts data out in the linear PCM
unsigned or 2’s complement format. It is tri-stated until the user
requests a CONVERT operation.
6
MISO
O
SPI Master In, Slave Out pin. Serial data line used to
communicate with SPI master. Pin is tri-state when SS =1.
7
XTAL2
O
CRYSTAL 2: This is the crystal oscillator output. It is the
inversion of XTAL1.
8
XTAL1
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be
driven by an external clock. The clock to the WTS701 processor
is configured by a clock configuration register, which is set by the
host processor during the initialization phase.
9,10
VSSD
G
Digital Ground pin.
11,12
VCCD
P
Positive Digital Voltage Supply pin. These pins carry noise
generated by internal clocks in the chip. They must be
independently bypassed to Digital Ground to ensure correct
device operation and not connected together.
13
INT
O
Interrupt Output; an open drain output that indicates that the
device wishes an interrupt service. The device can request an
interrupt when it finishes an operation or needs more data to
process. Under what conditions the device generates an
interrupt can be configured through the user configuration
registers. This pin remains LOW until a Read Interrupt command
is executed.
14
MOSI
I
SPI Master Out, Slave In. Serial data input from Master and
Open Drain
15
SS
I
SPI Slave Select input. This is an active LOW input used to
select the device to respond to an SPI transaction.
16
SCLK
I
SPI Serial clock input.
25
CS
I
Chip Select (active LOW) Pin must be LOW to access WTS701
device.
26
R/ B
O
Ready/busy signal; This pin defaults HIGH indicating the device
is ready for data transfer. The pin is driven LOW to handshake a
pause in SPI data transfer and Open Drain.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com