PC87303 datasheet(66/114 Pages) NSC

66 / 114 page

60 Serial Ports (Continued)

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character If it is 0 one Stop

bit is generated in the transmitted data If it is 1

when a 5-bit data length is selected one and a

half Stop bits are generated If it is logic 1 when

either a 6- 7- or 8-bit word length is selected two

Stop bits are generated The receiver checks the

first Stop bit only regardless of the number of

Stop bits selected

Bit 3

This bit is the Parity Enable bit When it is 1 a

Parity bit is generated (transmit data) or checked

(receive data) between the last data bit and Stop

bit of the serial data (The Parity bit is used to

produce an even or odd number of 1s when the

data bits and the Parity bit are summed)

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is 0 an odd number of logic 1s

is transmitted or checked in the data word bits and

Parity bit When parity is enabled and bit 4 is 1 an

even number of logic 1s is transmitted or checked

Bit 5

This bit is the Stick Parity bit When parity is en-

abled it is used in conjunction with bit 4 to select

Mark or Space Parity When LCR bits 3 4 and 5

are 1 the Parity bit is transmitted and checked as a

0 (Space Parity) If bits 3 and 5 are 1 and bit 4 is a

0 then the Parity bit is transmitted and checked as

1 (Mark Parity) If bit 5 is 0 Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART

When it is set to 1 the serial output (SOUT) is

forced to the Spacing state (0) The break is dis-

abled by setting bit 6 to 0 The Break Control bit

acts only on SOUT and has no effect on the trans-

mitter logic

Note that this feature enables the CPU to alert a

terminal If the following sequence is used no er-

roneous characters will be transmitted because of

the break

1 Wait for the transmitter to be idle (TEMT e 1)

2 Set break for the appropriate amount of time If

the transmitter will be used to time the break

duration then check that TEMT e 1 before

clearing the Break Control bit

3 Clear break when normal transmission has to

be restored

During the break the Transmitter can be used as

a character timer to accurately establish the break

duration by sending characters and monitoring

THRE and TEMT

Bit 7

This bit is the Divisor Latch Access Bit (DLAB) It

must be set high (logic 1) to access the Divisor

Latches of the Baud rate Generator during a Read

or Write operation or to have the Baud Out

(BOUT) signal appear on the BOUT pin It must be

set low (logic 0) to access any other register

PC87303 데이터시트(PDF) 66 Page - National Semiconductor (TI)

PC87303 데이터시트(HTML) 66 Page - National Semiconductor (TI)

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