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PC87309VLJ 데이터시트(PDF) 187 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC87309VLJ
상세설명  PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging
PDF  192 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87309VLJ 데이터시트(HTML) 187 Page - National Semiconductor (TI)

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Device Specifications
187
www.national.com
10.3.19 Enhanced Parallel Port 1.9 Timing
1. When WAIT is low, tWST19a and tWW19a are measured after WR or RD becomes active; else
tWST19a and tWW19a are measured after WAIT becomes low.
2. The PC87307VUL design guarantees that WRITE will not change from low to high before
DSTRB, or ASTRB, goes from low to high.
3. D7-0 is stable 15 nsec before WR becomes active.
Symbol
Parameter
Min
Max
Unit
tWW119a
WRITE Active from WR Active or WAIT Low1
45
nsec
tWW19ia
WRITE Inactive from WAIT Low
45
nsec
tWST19a
DSTRB or ASTRB Active from WR or RD Active or WAIT Low1 2
65
nsec
tWST19ia
DSTRB or ASTRB Inactive from WR or RD High
45
nsec
tWEST19
DSTRB or ASTRB Active after WRITE Active
10
nsec
tWPD19h
PD7-0 Hold after WRITE Inactive
0
nsec
tHRW19
IOCHRDY Active after WR or RD Active or Inactive after WAIT High
40
nsec
tWPDS19
PD7-0 Valid after WRITE Active3
15
nsec
tEPDW19
PD7-0 Valid Width
80
nsec
tEPD19h
PD7-0 Hold after DSTRB or ASTRB Inactive
0
nsec
tZWS19a
ZWS Valid after WR or RD Active
45
nsec
tZWS19h
ZWS Hold after WR or RD Inactive
0
nsec
WR
RD
D7-0
WRITE
DSTRB
ASTRB
PD7-0
WAIT
IOCHRDY
Valid
Valid
tWST19a
tHRW19
tHRW19
tWST19a
tWW19ia
tWPD19h
tWST19ia
tEPD19h
tEPDW19
or
tHRW19
tZWS19a
tZWS19h
tZWS19a
tZWS19h
ZWS
tWW19a
tWST19ia
tWST19a
{Note a}
{Note a}
tWW19a
{Note a}
tHRW19
tWPDS19
tWEST19
tWST19a



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