PC87311AVF datasheet(44/78 Pages) NSC

44 / 78 page

50 FDC Functional Description (Continued)

missing a clock or data pulse in the MFM or FM pattern A

secondary PLL is used to automatically calibrate the quarter

period delay line The secondary PLL also calibrates the

center frequency of the VCO

To eliminate the logic associated with controlling multiple

data rates the FDC supports each of the four data rates

(250 300 500 kbs and 1 Mbs) with a separate optimized

internal filter The appropriate filter for each data rate is au-

tomatically switched into the data separator circuit when the

data rate is selected via the Data Rate Select or Configura-

tion Control Register These filters have been optimized

through lab experimentation and are designed into the con-

troller to reduce the external component cost associated

with the floppy controller

The FDC has a dynamic window margin and lock range per-

formance capable of handling a wide range of floppy disk

drives Also the data separator will work well under a variety

of conditions including the high motor speed fluctuations of

floppy compatible tape drives

Figure 5-2 shows the floppy disk controller dynamic window

margin performance at the four different data rates Dynam-

ic window margin is the primary indicator of the quality and

performance level of the data separator This measurement

indicates how much motor speed variation (MSV) of the

drive spindle motor and bit jitter (or window margin) can be

tolerated by the data separator

MSV is shown on the x-axis of the dynamic window margin

graph MSV is translated directly to the actual data rate of

the data as it is read from the disk by the data separator

That is a faster than nominal motor will result in a higher

frequency in the actual data rate

The dynamic window margin performance curves also indi-

cate how much bit jitter (or window margin) can be tolerated

by the data separator This parameter is shown on the y-ax-

is of the graphs Bit jitter is caused by the magnetic interac-

tion of adjacent data pulses on the disk which effectively

shifts the bits away from their nominal positions in the mid-

dle of the bit window Window margin is commonly mea-

sured as a percentage This percentage indicates how far a

data bit can be shifted early or late with respect to its nomi-

nal bit position and still be read correctly by the data sepa-

rator If the data separator cannot correctly decode a shifted

bit then the data will be misread and a CRC will result

The dynamic window margin performance curves contain

two pieces of information 1) the maximum range of MSV

(also called ‘‘lock range’’) that the data separator can han-

dle with no read errors and 2) the maximum percentage of

window margin (or bit jitter) that the data separator can han-

dle with no read errors Thus the area under the dynamic

window margin curves in

Figure 5-2 is the range of MSV and

bit jitter that the FDC can handle with no read errors

TLF11362 – 10

FIGURE 5-1 FDC Data Separator Block Diagram

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