PC87311AVF datasheet(15/78 Pages) NSC

15 / 78 page

20 Configuration Registers (Continued)

Bit 3

When this bit is one the FDC can be accessed at the

address specified in FER 5

When this bit is zero ac-

cess to the FDC is blocked and it will be in power

down mode The FDC registers retain all data in power

down mode

Bit 4

When this bit is zero the PC87311A12 can control

two floppy disk drives directly without an external de-

coder When this bit is one the two drive select signals

and two motor enable signals from the FDC are en-

coded so that four floppy disk drives can be controlled

(see Table 2-4) Controlling four FDDs requires an ex-

ternal decoder The pin states shown in Table 2-4 are

a direct result of the bit patterns shown All other bit

patterns produce pin states that should not be decod-

ed to enable any drive or motor

Bit 5

This bit selects the primary or secondary FDC address

in the PC87312 In the PC87311A this bit selects the

primary or secondary FDC address when in the AT

mode In the XT mode it has no significance (see Ta-

ble 2-3)

Bit 6

When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7 When

it is zero access to the IDE interface is blocked the

IDE control signals (ie HCS0 HCS1 IDELO IDEHI)

are held in the inactive state and the IDED7 signal will

be in TRI-STATE

Bit 7

This bit selects the primary or secondary IDE address

in the PC87312 In the PC87311A this bit selects the

primary or secondary IDE address when in the AT

mode In the XT mode it has no significance (see Ta-

ble 2-3)

TABLE 2-3 Primary and Secondary Drive Address Selection

BIT 5

BIT 7

DRIVE

XT (Note)

Primary

Secondary

FDC

3F0 – 7h

FDC

370 – 7h

FDC

3F0 – 7h

IDE

1F0 – 7 3F6 3F7h

IDE

170 – 7 376-7h

IDE

320 – 3h

Note

PC87311A only

TABLE 2-4 Encoded Drive and Motor Pin Information (FER 4 e 1)

Digital Output Reg

Drive Control Pins

Decoded Functions

MTR1

MTR0

DR1

DR0

XXX

(Note 1)

Activate Drive 0 and Motor 0

(Note 1)

Activate Drive 1 and Motor 1

(Note 1)

Activate Drive 2 and Motor 2

(Note 1)

Activate Drive 3 and Motor 3

XXX

(Note 1)

Activate Drive 0 and Deactivate Motor 0

(Note 1)

Activate Drive 1 and Deactivate Motor 1

(Note 1)

Activate Drive 2 and Deactivate Motor 2

(Note 1)

Activate Drive 3 and Deactivate Motor 3

Note 1

When FER4 e 1 MTR1 will present a pulse that is the inverted image of the IOW strobe This inverted pulse will be active whenever an IO write to

address 3F2h or 372h takes place This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an

external latch (eg 74LS175) Address 3F2h will be used if the FDC is located at the primary address (FER5 e 0) and address 372h will be used if the FDC is

located at the secondary address (FER5 e 1) See the AC Electrical Characteristics (Section 92) for detailed timing

PC87311AVF 데이터시트(PDF) 15 Page - National Semiconductor (TI)

PC87311AVF 데이터시트(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

데이터시트 다운로드

링크 URL