PC97307 datasheet(125/218 Pages) NSC

125 / 218 page

125

Parallel Port (Logical Device 4)

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Bit 3 - ECP DMA Enable

0 - The DMA request signal (DRQ3-0) is set to TRI-

STATE and the appropriate acknowledge signal

(DACK3-0) is assumed inactive.

1 - The DMA is enabled and the DMA starts when bit 2

of ECR is 0.

Bit 4 - ECP Interrupt Mask

0 - An interrupt is generated on ERR assertion (the

high-to-low edge of ERR). An interrupt is also gen-

erated while ERR is asserted when this bit is

changed from 1 to 0; this prevents the loss of an in-

terrupt between ECR read and ECR write.

1 - No interrupt is generated.

Bits 7-5 - ECP Mode Control

These bits set the mode for the ECP device. See Sec-

tion 6.6 for a more detailed description of operation in

each of these ECP modes. The ECP modes are listed in

Table 6-9 and described in detail in Table 6-11.

TABLE 6-9. ECP Modes Encoding

ECR Bit Encoding

Mode Name

Bit 7

Bit 6

Bit 5

Standard

PS/2

Parallel Port FIFO

ECP FIFO

EPP Mode

FIFO Test

Conﬁguration

6.5.13

ECP Extended Index Register (EIR),

Offset 403h

The parallel port is partially configured by bits within the log-

ical device address space. These configuration bits are ac-

cessed via this read/write register and the Extended Data

perI/O Parallel Port Configuration register at index F0h of

logical device 4 is set to 1. See Section 2.7.1 on page 37.

The configuration bits within the parallel port address space

are initialized to their default values on reset, and not when

the parallel port is activated.

FIGURE 6-27. EIR Register Bitmap

Bits 2-0 - Second Level Offset

Data written to these bits is used as a second level off-

set for accesses to a specific control register. Second

level offsets of 00h, 02h, 04h and 05h are supported. At-

tempts to access registers at any other offset have no

effect.

TABLE 6-10. Second Level Offsets

000 - Access the Control0 register.

010 - Access the Control2 register.

100 - Access the Control4 register.

101 - Access the PP Confg0 register.

Bits 7-3 - Reserved

These bits are treated as 0 for offset calculations. Writ-

ing any other value to them has no effect.

These bits are read only. They return 00000 on reads

and must be written as 00000.

Second Level

Offset

Control

Described in

Section

00h

Control0

6.5.16 on page 126

02h

Control2

6.5.17 on page 126

04h

Control4

6.5.18 on page 127

05h

PP Confg0

6.5.19 on page 127

76543210

Reset

Required

ECP Extended Index

Offset 403h

Second Level Offset

Reserved

PC97307 데이터시트(PDF) 125 Page - National Semiconductor (TI)

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