PC97307 datasheet(22/218 Pages) NSC

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Signal/Pin Connection and Description

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WGATE

FDC

Output

Group 16

Write Gate (FDC) – This output signal enables the write circuitry of

the selected disk drive. WGATE is designed to prevent glitches

during power up and power down. This prevents writing to the disk

when power is cycled.

FDC

Input

Group 1

Write Protected – This input signal indicates that the disk in the

selected drive is write protected.

ISA-Bus

Input

Group 1

I/O Write – WR is an active low input signal that indicates a write

operation from the microprocessor to the controller.

WRITE

112

Parallel Port

Output

Group 23

Write Strobe – In EPP mode, this active low signal is a write strobe.

This signal is multiplexed with STB. See Table 6-12 on page 134 for

more information.

Clock

Input

Group 6

Clock In – A TTL or CMOS compatible 24 MHz or 48 MHz clock.

See Chapter 11.

X1C

RTC

Input

Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)

crystal oscillator ampliﬁer.

X2C

RTC

Output

Crystal 2 Slow – Output signal from the internal Real-Time Clock

(RTC) crystal oscillator ampliﬁer.

XD7,6,

XD1,0

78, 77

72, 71

X-Bus

I/O

Group 9

X-Bus Data – These bidirectional signals hold the data in the X Data

Buffer (XDB).

XD7 is multiplexed with IRSL1 and ID1.

XD6 is multiplexed with IRSL2, SELCS and GPIO21.

XD5-2 are multiplexed with GPIO27-24, respectively.

XD1,0 are multiplexed with CS2,1 respectively.

See Table 1-2 on page 23.

XD5-2

76-73

X-Bus

I/O

Group 10

XDCS

X-Bus

Input

Group 7

X-Bus Data Buffer (XDB) Chip Select – This signal enables and

disables the bidirectional XD7-0 data buffer signals.

This signal is multiplexed with RING. See Table 1-2 on page 23.

XDRD

X-Bus

Input

Group 1

X-Bus Data Buffer (XDB) Read Command – This signal controls

the direction of the bidirectional XD7-0 data buffer signals.

This signal is multiplexed with ID3. See Table 1-2 on page 23.

ZWS

ISA-Bus

Output

Group 22

Zero Wait State – When this open-drain output signal is activated

(driven low), it indicates that the access time can be shortened, i.e.,

zero wait states.

ZWS is never activated (driven low) on access to SuperI/O chip

conﬁguration registers (including during the Isolation state) or on

access to the parallel port in SPP or EPP 1.9 mode.

ZWS is always activated (driven low) on access to the parallel port in

ECP mode.

Assertion of ZWS on access to a parallel port in EPP 1.7 mode is

controlled by bit 3 of the Control2 register (at second level offset 02h)

of the parallel port (accessed by the Index and Data registers at

base+403h and base+404h). See page 127.

Bit 0 of the SuperI/O Conﬁguration 1 register (at index 21h) controls

assertion of ZWS on access to any other addresses of the part. See

page 35.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

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