PC97307 datasheet(152/218 Pages) NSC

152 / 218 page

152

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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TABLE 7-12. Bits Cleared On Fallback

FIGURE 7-19. LBGD(L) Register Bitmap

FIGURE 7-20. LBGD(H) Register Bitmap

7.11.13 Link Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

7.12 BANK 2 – EXTENDED CONTROL AND STATUS

REGISTERS

Bank 2 contains two alternate Baud Generator Divisor ports

and the Extended Control Registers (EXCR1 and EXCR2).

UART Mode & LOCK bit before Fallback

Extended

Mode

LOCK = x

Non-Extended

Mode

LOCK = 0

Non-Extended

Mode

LOCK = 1

MCR

2 to 7

none

EXCR1

0, 5 and 7

5 and 7

none

EXCR2

0 to 5

none

IRCR1

2 and 3

none

76543210

Reset

Required

Low Byte port

(LBGD(L))

Bank 1,

Least Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 00h

76543210

Reset

Required

High Byte port

(LBGD(H))

Bank 1,

Most Significant Byte

Legacy Baud Generator Divisor

of Baud Generator

Offset 01h

TABLE 7-13. Bank 2 Register Set

7.12.1

Baud Generator Divisor Ports, LSB (BGD(L))

and MSB (BGD(H)), Bank 2, Offsets 00h and 01h

These ports perform the same function as the Legacy Baud

Divisor Ports in Bank 1 and are accessed identically to them,

but do not change the operation mode of the module when ac-

cessed. Refer to Section 7.11.12 on page 151 for more detail.

Use these ports to set the baud rate when operating in Extend-

ed mode to avoid fallback to a Non-Extended operation mode,

i.e., 16550 compatible.When programming the baud rate, writ-

ing to BGDH causes the baud rate to change immediately.

FIGURE 7-21. BGD(L) Register Bitmap

FIGURE 7-22. BGD(H) Register Bitmap

Offset Register

Name

Description

00h

BGD(L)

Baud Generator Divisor Port (Low byte)

01h

BGD(H)

Baud Generator Divisor Port (High byte)

02h

EXCR1

Extended Control Register 1

03h

LCR/BSR

Link Control/ Bank Select Register

04h

EXCR2

Extended Control Register 2

05h

Reserved

06h

TXFLV

TX_FIFO Level

07h

RXFLV

RX_FIFO Level

76543210

Reset

Required

Low Byte Port

(BGD(L))

Bank 2,

Least Significant Byte

Baud Generator Divisor

of Baud Generator

Offset 00h

76543210

Reset

Required

High Byte Port

(BGD(H))

Bank 2,

Most Significant Byte

of Baud Generator

Baud Generator Divisor

Offset 01h

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