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PC97307 데이터시트(PDF) 165 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC97307
상세설명  PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
PDF  218 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC97307 데이터시트(HTML) 165 Page - National Semiconductor (TI)

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165
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
www.national.com
Bits 2-0 - Reserved
Read/write 0.
Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS)
This bit determines the direction of the ID/IRSL2 and
ID/IRSL1 pins.
0 - Pins’ direction is input.
1 - Pins’ direction is output.
Bit 4 - IRRX Signal Invert (RXINV)
This bit supports optical transceivers with receive signals
of opposite polarity (active high instead of active low).
When set to 1 an inverter is put on the path of the input
signal of the receiver.
Bit 5 - ID0/IRSL0/IRRX2 Pin Direction Select (IRSL0_DS)
This
bit
determines
the
direction
of
the
ID0/
IRSL0/IRRX2 pin. See Table 7-31 on page 165.
0 - Pin’s direction is input.
1 - Pin’s direction is output.
Bit 6 - Reserved
Read/write 0.
Bit 7 - Automatic Module Configuration (AMCFG)
When set to 1, this bit enables automatic infrared con-
figuration.
a. IRCFG4 is in bank 7, offset 07h. It is
described on page 164.
b. AUX_IRRX (bit 4 of IRCR2) is described on
page 158.
TABLE 7-31. Infrared Receiver Input Selection
Bit 5 of IRCFG4a
(IRSL0_DS)
Bit 4 of IRCR2
(AUX_IRRX)b
Selected IRRX
0
0
IRRX1
0
1
IRRX2
1
0
IRRX1
11
1
7.18 UART2 REGISTER WITH FAST IR REGISTER
BITMAPS
76543210
Reset
Required
Receiver Data
Register (RXD)
Bank 0,
Received Data
Read Cycles
Offset 00h
76543210
Reset
Required
Transmitter Data
Register (TXD)
Bank 0,
Transmitted Data
Write Cycles
Offset 00h
76543210
Reset
Required
0
0
0
0
0
0
0
0
0
LS_IE or TXUR_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
RXHDL_IE
TXLDL_IE
MS_IE
Interrupt Enable
Register (IER)
Bank 0,
Extended Mode
Offset 01h
76543210
Reset
Required
1
0
0
0
0
0
0
0
0
0
Non-Extended Modes, Read Cycles
IPR1 - Interrupt Priority 1
Reserved
Reserved
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
Event Identification
IPR0 - Interrupt Priority 0
RXFT - RX_FIFO Time-Out
Bank 0,
Register (EIR)
Offset 02h
IPF - Interrupt Pending



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