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PC87332VLJ 데이터시트(PDF) 92 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 PC87332VLJ
상세설명  PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
PDF  98 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87332VLJ 데이터시트(HTML) 92 Page - National Semiconductor (TI)

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90 Electrical Characteristics (Continued)
938 DMA Timing
Symbol
Parameter
Min
Max
Units
tKI
FDACK or PDACK Inactive Pulse Width
25
ns
tKK
FDACK or PDACK Active Pulse Width
65
ns
tKQ
FDACK Active Edge to FDRQ Inactive (Note 1)
65
ns
PDACK Active Edge to PDRQ Inactive (Note 1)
tQK
FDRQ to FDACK Active Edge
10
ns
PDRQ to PDACK Active Edge
tQP
FDRQ Period (FDC-Burst DMA)
8 c tDRP
m
s
PDRQ Period (ECP)
330
m
s
tQQ
FDRQ or PDRQ Inactive Non-Burst Pulse Width
300
400
ns
tQR
FDRQ to RD or WR Active
15
ns
PDRQ to RD or WR Active
tQW
FDRQ to End of RD WR (Note 1)
(8 c tDRP) b (16 c tICP)
m
s
(FDRQ Service Time)
tQT
FDRQ to TC Active (Note 1)
(8 c tDRP) b (16 c tICP)
m
s
(FDRQ Service Time)
tRQ
RD WR Active Edge to FDRQ or PDRQ Inactive (Note 2)
65
ns
tTQ
TC Active Edge to FDRQ or PDRQ Inactive
75
ns
tTT
TC Active Pulse Width
50
ns
Note 1
For FDC DMA Values shown are with the FIFO disabled or with FIFO enabled and THRESH e 0 For non-zero values of THRESH add (THRESH c 8 c
tDRP) to the values shown
For ECP DMA Value shown is with the FIFO disabled For FIFO enabled add (192 c TCP) to the value shown (assuming IOCHRDY e 1)
Note 2
The active edge of RD or WR and TC is recognized only when FDACK or PDACK is active
TLC11930 – 33
FIGURE 9-8 DMA Timing
92



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