L9659 datasheet(17/51 Pages) STMICROELECTRONICS

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L9659

Electrical specifications

Doc ID 022048 Rev 2

17/51

2.4.3

SPI timing

All SPI timing is performed with a 150 pF load on MISO unless otherwise noted

4.9V

 V

DD  5.1V; 7V  VRESX  37V; 7V  VSDIAG  37V; FEN1 = FEN2 = FEN3 = FEN4 =

VDD; R_REF = 10K, ±1%, 100PPM; -40°C  TA  +95°C; C_VRES0_1  68nF;

C_VRES2_3

 68nF; C_VRES4_5  68nF; C_VRES6_7  68nF; unless other specified.

Table 8.

SPI timing - DC electrical characteristics

No.

Symbol

Parameter

Min.

Typ.

Max.

Unit

fop

Transfer frequency

5.50

MHz

tSCK

SCLK Period

181

tLEAD

Enable Lead Time

tLAG

Enable Lag Time

tSCLKHS

SCLK, High Time

tSCLKLS

SCLK, Low Time

tSUS

MOSI, Input Setup Time

tHS

MOSI, Input Hold Time

MISO, Access Time

tDIS

(1)

MISO, Disable Time

100

tVS

MISO, Output Valid Time

tHO (1)

MISO, Output Hold Time

tRO

Rise Time (Design Information)

tFO

Fall Time (Design Information)

tCSN

CS_D, Negated Time

640

tCLKN

Time between CS rising edge and first transition

of SCLK must be higher than tCLKN. It happens

when multiple devices are connected to the

same SCLK and MOSI but with different chip

select.

500

Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance

on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable

time, and minimum capacitance on MISO is the worst case for output hold time.

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