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TNETV1647GSTZWT 데이터시트(PDF) 171 Page - Texas Instruments |
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TNETV1647GSTZWT 데이터시트(HTML) 171 Page - Texas Instruments |
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171 / 236 page ![]() PCLK (Positive Edge Clocking) PCLK (Negative Edge Clocking) 7, 9 HD/VD CCD[15:0] 8, 10 11, 13 12, 14 5 6 C_WE/C_FIELD PCLK (Positive Edge Clocking) 15 16 23 24 CCD[15:0] C_WE PCLK (Negative Edge Clocking) TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Figure 6-47. VPFE (CCD) Slave Mode Input Data Timing Table 6-55. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 6-48) 1.05 V and 1.2 V NO. UNIT MIN MAX 15 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns 16 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns 23 tsu(CWEV-PCLK) Setup time, C_WE valid before PCLK edge 3 ns 24 th(PCLK-CWEV) Hold time, C_WE valid after PCLK edge 2 ns (1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. Figure 6-48. VPFE (CCD) Master Mode Input Data Timing Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 171 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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