TNETV1647GSTZWT datasheet(182/236 Pages) TI1

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TMS320DM6441

SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010

www.ti.com

Table 6-63. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and

Data Output With Respect to VCLK(1) (2) (see Figure 6-53)

1.05 V

1.2 V

NO.

PARAMETER

MODE(3)

UNIT

MIN

MAX

MIN

MAX

tc(VCLK)

Cycle time, VCLK

13.33

160

13.33

160

Pulse duration, VCLK high

H - 1.3(4)

H - 0.3(4)

H - 1.3(4)

H - 0.3(4)

(positive-edge clocking)

tw(VCLKH)

Pulse duration, VCLK high

L - 1.3(4)

L - 0.3(4)

L - 1.3(4)

L - 0.3(4)

(negative-edge clocking)

Pulse duration, VCLK low

L + 0.3(4)

L + 1.3(4)

L + 0.3(4)

L + 1.3(4)

(positive-edge clocking)

tw(VCLKL)

Pulse duration, VCLK low

H + 0.3(4)

H + 1.3(4)

H + 0.3(4)

H + 1.3(4)

(negative-edge clocking)

tt(VCLK)

Transition time, VCLK

Delay time, VCLKIN high to

td(VCLKINH-VCLKH)

VCLK high

Delay time, VCLKIN low to

td(VCLKINL-VCLKL)

VCLK low

Delay time, VCLK negative edge

9.1

7.5

to VCTL valid

td(VCLK-VCTLV)

Delay time, VCLK positive edge

6.9

to VCTL valid

Delay time, VCLK negative edge

2.3

to VCTL invalid

td(VCLKL-VCTLIV)

Delay time, VCLK positive edge

1.9

1.5

to VCTL invalid

Delay time, VCLK negative edge

6.8

to VDATA valid

td(VCLK-VDATAV)

Delay time, VCLK positive edge

7.3

6.3

to VDATA valid

RGB

2.8

2.1

Delay time, VCLK negative edge

to VDATA invalid

YCC

2.8

2.5

td(VCLKL-VDATAIV)

RGB

2.3

1.9

Delay time, VCLK positive edge

to VDATA invalid

YCC

2.6

2.1

(1)

The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the

rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.

(2)

VCLKIN = PCLK or VPBECLK

(3)

RGB and YCC modes utilize different data pins. RGB mode uses data pins: R[7:0], G[7:0], and B[7:0]. YCC mode uses data pins:

COUT[7:0] and YOUT[7:0].

(4)

H and L are the high and low pulse widths of the input clock to the VPBE, respectively. For example, if VPBECLK is used as the input

clock and it has a high pulse duration of 6.67 ns, the resulting high pulse duration of VCLK, if positive-edge clocking is selected, will be a

MAX of 6.37 ns and a MIN of 5.27 ns.

182

Peripheral and Electrical Specifications

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