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TNETV1644ZDU6 데이터시트(PDF) 165 Page - Texas Instruments

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부품명 TNETV1644ZDU6
상세설명  Digital Media Processor
PDF  306 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-1. DM6437 Power and Clock Domains
Power Domain
Clock Domain
Peripheral/Module
Always On
CLKIN
UART0
Always On
CLKIN
UART1
Always On
CLKIN
HECC
Always On
CLKIN
I2C
Always On
CLKIN
Timer0
Always On
CLKIN
Timer1
Always On
CLKIN
Timer2
Always On
CLKIN
PWM0
Always On
CLKIN
PWM1
Always On
CLKIN
PWM2
Always On
CLKDIV3
DDR2
Always On
CLKDIV3
VPSS
Always On
CLKDIV3
EDMA
Always On
CLKDIV3
PCI
Always On
CLKDIV3
SCR
Always On
CLKDIV6
GPSC
Always On
CLKDIV6
LPSCs
Always On
CLKDIV6
PLLC1
Always On
CLKDIV6
PLLC2
Always On
CLKDIV6
Ice Pick
Always On
CLKDIV6
EMIFA
Always On
CLKDIV6
HPI
Always On
CLKDIV6
VLYNQ
Always On
CLKDIV6
EMAC
Always On
CLKDIV6
McASP0
Always On
CLKDIV6
McBSP0
Always On
CLKDIV6
McBSP1
Always On
CLKDIV6
GPIO
Always On
CLKDIV1
C64x+ CPU
Table 6-2. DM6437 Clock Domains
DOMAIN CLOCK
FIXED RATIO vs.
EXAMPLE
SUBSYSTEM
CLOCK DOMAIN
SOURCE
SYSCLK1 FREQUENCY
FREQUENCY (MHz)
Peripherals (CLKIN Domain)
CLKIN
PLLC1 AUXCLK(1)
–
27 MHz
DSP Subsystem
CLKDIV1
PLLC1 SYSCLK1
1:1
594 MHz
EDMA3
CLKDIV3
PLLC1 SYSCLK2
1:3
198 MHz
VPSS
CLKDIV3
PLLC1 SYSCLK2
1:3
198 MHz
Peripherals (CLKDIV3 Domain)
CLKDIV3
PLLC1 SYSCLK2
1:3
198 MHz
Peripherals (CLKDIV6 Domain)
CLKDIV6
PLLC1 SYSCLK3
1:6
99 MHz
(1)
PLLC1 AUXCLK runs at exactly the same frequency as the device clock source from the MXI/CLKIN pin.
The CLKDIV1:CLKDIV3:CLKDIV6 ratio must be strictly followed by programming the PLL Controller 1
(PLLC1) PLLDIV1, PLLDIV2, and PLLDIV3 registers appropriately (see Table 6-3).
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
165



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