 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
TNETV1644ZDU6 데이터시트(PDF) 211 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV1644ZDU6 데이터시트(HTML) 211 Page - Texas Instruments |
|
|
211 / 306 page  DDR_CLK 1 6.10 Video Processing Sub-System (VPSS) Overview 6.10.1 Video Processing Front-End (VPFE) TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller(1)(2)(see Figure 6-18) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. PARAMETER UNIT MIN MAX 1 tc(DDR_CLK) Cycle time, DDR_CLK 6 8 ns (1) DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time. (2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range. Figure 6-18. DDR2 Memory Controller Clock Timing The DM6437 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital LCD panels, HDTV video encoders, etc. The VPSS register memory mapping is shown in Table 6-28. Table 6-28. VPSS Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM Description 0x01C7 3400 PID Peripheral Revision and Class Information 0x01C7 3404 PCR VPSS Control Register 0x01C7 3408 - Reserved 0x01C7 3508 SDR_REG_EXP SDRAM Non Real-Time Read Request Expand 0x01C7 350C - - Reserved 0x01C7 3FFF The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC), Preview Engine, Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide DM6437 with a powerful and flexible front-end interface. These modules are briefly described below: • The CCDC provides an interface to image sensors and digital video sources. • The Preview Engine is a parameterized hardwired image processing block which is used for converting RAW color data from a Bayer pattern to YUV 4:2:2. • The Resizer module re-sizes the input image data to the desired display or video encoding resolution. • The H3A module provides control loops for Auto Focus (AF), Auto White Balance (AWB) and Auto Exposure (AE). • The Histogram module bins input color pixels, depending on the amplitude, and provides statistics required to implement various 3A (AE/AF/AWB) algorithms and tune the final image/video output. The VPFE register memory mapping is shown in Table 6-29. Table 6-29. VPFE Register Address Range Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C7 0400 – 0x01C7 07FF CCDC VPFE – CCD Controller 0x01C7 0800 – 0x01C7 0BFF PREV VPFE – Preview Engine/Image Signal Processor 0x01C7 0C00 – 0x01C7 09FF RESZ VPFE – Resizer Submit Documentation Feedback Peripheral Information and Electrical Specifications 211 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
