TNETV1644ZDU6 datasheet(214/306 Pages) TI1

214 / 306 page

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

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• Support for an image that is downsampled by 2x in the horizontal direction (with and without phase

correction). In this case, the image is 2/3 populated instead of the conventional 1/3 colors.

• Support for an image that is downsampled by 2x in both the horizontal and vertical direction. In this

case, the image is fully populated instead of the conventional 1/3 colors.

• Programmable RGB-to-RGB blending matrix (9 coefficients for the 3x3 matrix).

• Fully programmable gamma correction (1024 entries for each color held in an on-chip RAM).

• Programmable color conversion (RGB to YUV) coefficients (9 coefficients for the 3x3 matrix).

• Luminance enhancement (non-linear) and chrominance suppression & offset.

The Preview Engine register memory mapping is shown in Table 6-31.

Table 6-31. Preview Engine Register Descriptions

HEX ADDRESS RANGE

DESCRIPTION

0x01C7 0800

PID

Peripheral Revision and Class Information

0x01C7 0804

PCR

Peripheral Control Register

0x01C7 0808

HORZ_INFO

Horizontal Information/Setup

0x01C7 080C

VERT_INFO

Vertical Information/Setup

0x01C7 0810

RSDR_ADDR

Read Address From SDRAM

0x01C7 0814

RADR_OFFSET

Line Offset for the Read Data

0x01C7 0818

DSDR_ADDR

Dark Frame Address From SDRAM

0x01C7 081C

DRKF_OFFSET

Line Offset for the Dark Frame Data

0x01C7 0820

WSDR_ADDR

Write Address to the SDRAM

0x01C7 0824

WADD_OFFSET

Line Offset for the Write Data

0x01C7 0828

AVE

Input Formatter/Averager

0x01C7 082C

HMED

Horizontal Median Filter

0x01C7 0830

Noise Filter

0x01C7 0834

WB_DGAIN

White Balance Digital Gain

0x01C7 0838

WBGAIN

White Balance Coefficients

0x01C7 083C

WBSEL

White Balance Coefficients Selection

0x01C7 0840

CFA

CFA Register

0x01C7 0844

BLKADJOFF

Black Adjustment Offset

0x01C7 0848

RGB_MAT1